The present invention relates generally to processing systems and in particular the present invention relates to a method and a system to allow for symmetric memory population.
Modem processing systems, such as personal computers include memory for storing data. Because the amount of memory needed by a user of the processing system is not know when the system is manufactured, the systems are often designed to allow the memory to be expanded. In a typical processing system, such as a personal computer (PC), the memory can be expanded by adding additional memory modules. For example, a processing system can be provided which has a memory card that includes a number of expansion sockets for accepting memory modules.
In some processing systems, the memory expansion sockets must be populated in pairs to obtain increased bandwidth. When populated in pairs, the memory needs to be populated in a manner which maintains symmetry between memory channels. The symmetry is defined by the memory communication channels, and not by the physical location of the expansion sockets. Because the memory communication channels and the physical location of the expansion sockets do not necessary correspond, a problem can be created when a user adds additional memory modules.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and system which allow for symmetric memory population in a processing system.
In one embodiment, a processing system comprises a memory controller having a first memory communication channel and a second memory communication channel, and a memory card coupled to the memory controller. The memory card comprises a plurality of memory sockets for receiving memory devices, a first memory repeater circuit coupled to the first memory communication channel, and a second memory repeater circuit coupled to the second memory communication channel. The first and second memory repeater circuits each comprise first and second memory communication channel output connections. A processor is coupled to the memory controller to instruct the memory controller to modify an output address signal provided on the second memory communication channel. The output address signal identifies either the first or second memory communication channel output connections of the second memory repeater circuit.
In another embodiment, a processing system comprises a memory controller having a first memory communication channel output connection and a second memory communication channel output connection, and a memory card coupled to the memory controller. The memory card comprises a plurality of memory sockets for receiving memory devices, a first memory repeater circuit coupled to the first memory communication channel output connection, and a second memory repeater circuit coupled to the second memory communication channel output connection. The first and second memory repeater circuits each comprise first and second memory communication channel output connections. A signal propagation time from the memory controller first memory communication channel output connection to an input of the first memory repeater circuit is substantially equal to a signal propagation time from the memory controller second memory communication channel output connection to an input of the second memory repeater circuit. A processor is coupled to the memory controller to instruct the memory controller to invert a single bit output address signal provided on the second memory communication channel. The output address signal identifies a communication path with the memory sockets through either the first or second memory communication channel output connections of the second memory repeater circuit.